Circuito Digital para Redução da Sobreposição de Sinais num Detector de Partículas

Igo A. S. Luz, Joao Paulo B. S. Duarte, Eduardo F. Simas Filho, Paulo C. M. A. Farias, ˜ Luciano M. de Andrade Filho, Jose M. de Seixas

DOI: 10.14209/sbrt.2018.98

Evento: XXXVI Simpósio Brasileiro de Telecomunicações e Processamento de Sinais (SBrT2018)

Keywords: FPGA Digital Filter Deconvolution Signal Processing Calorimeter

Abstract

The pileup phenomenon is related to the rate of occurrence of the events and the response time of the sensors. In the field of particle detectors, the current ATLAS hadronic calorimeter instrumentation system, one of the LHC detectors, is not effective in the reconstruction of the signals affected by the pileup. This work proposes the implementation of a digital circuit responsible for the reconstruction of the ATLAS calorimeter signals. The functional verification of the circuit was performed through a simulated data set. The analysis of the results validated that the proposed solution met the functional requirements.

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