Método Iterativo de Representação Esparsa Implementado em FPGA para Aplicação em Calorimetria

The LHC particle accelerator has been undergoing an upgrade process, producing the effect known as pile-up in the reading electronics of the detectors. As the algorithm currently used to estimate the amplitude of the signals generated in these collisions is not tolerant to this effect, this work proposes the implementation in hardware of an iterative method based on a variant of the Separable Surrogate Functionals method that retrieves the information from the amplitude of the overlapping signals within an acquisition window. Such implementation allows dozens of channels to be implemented in parallel within a single FPGA, in addition to respecting the operating latency required for its online implementation.