Hardware-Friendly Implementation of Soft Information Set Decoders

This article has two main purposes: (i) to introduce and evaluate a modified version of the Dorsch soft decoding algorithm for block codes, based on information sets, and (ii) to examine the complexity of implementing this kind of decoder in hardware (more specifically, in FPGA devices). The modifications introduced in the algorithm lead to an optimized circuit size when the algorithm is implemented in hardware. Indeed, the physical implementation and its detailed analysis represent a major departure from traditional decoder analysis, increasingly important as more frequently such specialized functions are embedded into the hardware, in top-performance systems. It is demonstrated that, in the worst case, n – dmin + 1 iterations suffice to find the most reliable information set, from which only a very small fraction of all 2k possible candidate codewords needs to be tested to achieve near maximum likelihood decoding (MLD) performance. These conclusions are confirmed by simulations on a C(48, 24, 12) block code, then used as guidelines in the physical implementations of several decoders, in order to test their real-time operation. A detailed circuit diagram is presented, along with experimental results indicating the number of logic cells and registers needed to implement the decoder in a high-end FPGA, for various code sizes.