A Low-Cost Implementation of High-Order Square M-QAM Detection/Demodulation in a FPGA Device

This paper outlines a low-cost technique for detection/demodulation of high-order square M-ary quadrature amplitude modulation (M-QAM), M = 4, 16, 64, 256, 1024, and 4096, in a field programmable gate array (FPGA) device. Hence, it is very interesting for advancing high-speed power line communication technology. The proposed technique is based on a so-called heuristic decision region approach combined with a nonlinear function that allows to simplify the hardware implementation of detection and demodulation for a high-order square M-QAM symbols. The performance evaluation of the proposed technique is carried out when the channel is additive white Gaussian noise (AWGN) and additive impulsive Gaussian noise (AIGN). The attained results, in terms of bit error rate vs. energy per bit to noise power spectral density ratio (Eb/N0), indicate that the use of the proposed technique offers reduced performance losses. Also, its implementation in a FPGA device demands the lowest hardware resource and latency.