Arquitetura para o Multiplicador de Mastrovito Utilizando Circuitos de Limiar Linear

Andresso da Silva, Francisco M. Assis, Marlo Santos

DOI: 10.14209/sbrt.2019.1570558842

Evento: XXXVII Simpósio Brasileiro de Telecomunicações e Processamento de Sinais (SBrT2019)

Keywords:

Abstract

This paper presents an architecture for the Mastrovito multiplier using linear threshold circuits. Optimal irreducible polynomials are determined for the construction of the Mastrovito multiplier in finite field GF(2^m), for 1<m<17. The proposed architecture provides minor theoretical spatial complexity. However, when using the optimal irreducible polynomials, the proposed architecture will present minor spatial complexity for m>11 when compared to other architectures that use linear threshold circuits.

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