Contribuições ao Algoritmo A-SPADE Visando a Implementação de um Declipper em FPGA

This paper presents contributions to the A-SPADE algorithm, for the purpose of implementing a audio Declipper in FPGA. An approach that accelerates A-SPADE is proposed, originating the ATA-SPADE algorithm. Such an approach showed that ATA-SPADE is much faster than A-SPADE, showing equivalent performance. A clipping level estimation algorithm is also proposed. The presented algorithms constitute the main components of a Declipper. The proposed Declipper is implemented in FPGA and has its performance proven in a development kit