Redução de profundidade de lógica de hardware para codificação de LDPC

Alexandre Felipe, André L.N. Souza

DOI: 10.14209/sbrt.2017.36

Evento: XXXV Simpósio Brasileiro de Telecomunicações e Processamento de Sinais (SBrT2017)

Keywords: Low-density parity-check codes LDPC Latency Encoding

Abstract

Low-density Parity-check codes constructed for co- ding with linear computational complexity normally generate encoder hardware with high logical depth. This work indicates strategies to manipulate a triangular equation system in order to reduce the non-parallelizable stages, and consequently lower enconding latency, allowing faster bit rates.

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