FPGA-Embedded Machine Learning Equalizer for a MIMO BPSK System on a ZCU104 MPSoC

This paper reports an FPGA implementation of a quantized neural equalizer for a real-valued MIMO/BPSK link. A synthetic channel emulator generates fixed-channel 2 × 2 and 4 × 4 MIMO data, and a fully connected quantized network is trained with Brevitas, compiled with FINN, and validated on a Xilinx ZCU104 MPSoC. We evaluate input, weight, acti- vation quantization, network size, resource use, and hardware throughput. On 2 × 2 BPSK at 12 dB, a 2W2A, 8 × 8 × 8 model reaches 99.99% software and hardware accuracy with 4.44 Msamples/s on board - the highest measured throughput among all evaluated configurations. A network capacity threshold is identified: the 4 × 4 × 4 model is the smallest architecture achieving near-optimal accuracy, while the 2 × 2 × 2 model fails to learn a useful equalization mapping, achieving accuracy well below any practical operating point for a four-class problem.