Quantized CNV Equalization for MIMO Channels with Memory on a Zynq FPGA

Embedded machine learning enables latency sensitive signal processing at the network edge, but neural receivers on small FPGA platforms require careful quantization and hardware co-design. This paper presents a quantized convolutional neural network (CNN) equalizer for a real-valued 2 x 2 BPSK MIMO channel with finite memory, implemented on a Digilent Zybo-Z7-20 Zynq-7020 board using Brevitas, QONNX, FINN, Vivado and PYNQ. In this work, CNV denotes a FINN-compatible quantized CNN topology used for FPGA-oriented dataflow synthesis. We evaluate input, weight and activation bit widths, compare the selected hardware design against memory-aware ZF and LMMSE references, and analyze the effect of increasing the channel-memory span. The selected compact design reaches 96.19% hardware vector accuracy at 12 dB and approximately 1.32 Msamples/s. The experiments use pre-generated data and a fixed channel realization; therefore, the results represent an embedded FPGA proof of concept rather than validation of cross-channel or over-the-air robustness.