Implementação Eficiente de Filtros Volterra Explorando Abordagens de Posto Reduzido e Caracterı́sticas de Hardware

This paper presents a new approach for obtaining efficient implementations of Volterra filters. Such an approach is based on exploiting the different significance levels of the branches of reduced-rank Volterra structures, aiming to define individual word sizes for the implementation of each branch. In this way, significant reductions of computational cost can be obtained, especially for implementations carried out using field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). Results obtained from a case study are presented, demonstrating the effectiveness of the proposed approach.