Implementação em FPGA de Geradores de Números Pseudo-aleatórios sobre Anéis de Inteiros

An effective way to design pseudo-random number generators makes use of chaotic systems, taking advantage of their determinism associated with an output that looks random in spite of its easy generation. The implementation of these systems is facilitated when they are defined on suitable discrete structures, such as integer rings. In this work, we propose an optimized architecture for pseudo-random number generators based on Arnold's Cat map over the ring Z 3 m. An arithmetic unit is specified using binary-coded ternary representation. Finally, the PRNG is implemented using the Montgomery modular multiplier, which is compared with the proposal through the implementation of both in FPGA and the evaluation of the corresponding hardware consumptions.