FPGA implementation of a de-noising using Haar level 5 wavelet transform

This paper proposes an implementation in Field Programmable Gate Array (FPGA) of a de-noising using Haar wavelet transform. For this a signal with noise was applied at a Haar level 5 Discrete Wavelet Transform (DWT) through an threshold and then through an Inverse Wavelet transfom (IDWT). The design procedure has been designed using the Electronic Design Automation (EDA) tools for system design on FPGA. Simulation, synthesis and implementation on the FPGA target technology has been realized.