Arquitetura de Hardware Baseada no Algoritmo NLMS para a Extração de Sinais FECG

Patricia U. L. da Costa, Sérgio José Melo de Almeida, Eduardo da Costa

DOI: 10.14209/SBRT.2020.1570658147

Evento: XXXVIII Simpósio Brasileiro de Telecomunicações e Processamento de Sinais (SBrT2020)

Keywords: Sinais FECG algoritmo NLMS arquitetura de hardware

Abstract

This work presents a hardware architecture for the extraction of fetal electrocardiogram (FECG), based on the adaptive algorithm NLMS (Normalized Least Mean Square). Sensors positioned in the abdomen and maternal chest, capture the signals processed by hardware, seeking to identify the fetal heartbeat, canceling the interferences from the maternal electrocardiogram. We used performance parameters to evaluate the proposed architecture. The results showed that the architecture with 32 bits represents an optimum point between area and power dissipation, with small variations in error values, compared to other architectures with different bit-width.

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