FPGA Implementation of Farrow Structure for Time Interleaved Analog to Digital Converter Clock Skew Compensation

In modern wireless communication systems, TIADC arises as a good candidate for applications with high sampling rate and moderate power consumption requirements. However the performance of TIADC is impaired due to clock skew between the various ADCs. Clock skew performance degradation can be mitigated by fractional delay filters. Focusing on the clock skew mitigation this paper presents a fractional delay filter implemented in FPGA, based on Farrow structure. The procedure used for TIADC modeling and implementation of digital filter in FPGA is presented in detail.