Implementação em FPGA de um Método Recursivo de Deconvolução Aplicado em Calorímetros Operando a Alta Taxa de Eventos

The LHC particle accelerator has undergone an update process, producing the effect known as pile-up (overlapping signals) in the Experiment frontend electronics. As the algorithm currently used for the reconstruction of the energy generated in these collisions is not tolerant to this effect, this work proposes the hardware implementation of an iterative method based on a variant of Descending Gradient that recovers the information of the amplitude of the signals superimposed within an acquisition window. With this implementation dozens of channels can be implemented in parallel within a single FPGA, in addition to respecting the required operating latency to the ATLAS acquisition system.